SOC Interconnect Verification Challenge

Kushal Patel

Abstract


With increasing numbers of CPU cores, multimedia subsystems and communication IPs in todays System-on-Chips, the main SoC interconnects, crossbars or networks-on-chip fabrics become key components of the system. In addition, IP reuse and Network-on-Chip (NoC) generation solutions have enabled the conception of new SoC architectures within a few months if not only weeks. The verification of the SoC bus interconnects faces the challenge of verifying the correct routing of transactions as well as security and protection modes, power management features, virtual address space and bus protocol translations while still reaching project milestones. This paper describes the authors experiences in verifying multi-protocol SoC interconnects, it explains the pitfalls of such verification and describes a solution to allow easy reconfiguration of a generic verification environment. We show how issues have been resolved and propose a generic approach for SoC interconnect verification.


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