Performance Evaluation of CMOS based Adders and Comparative analysis of Speed, Delay and Power Dissipation

Jasleen Chaudhary, Birinderjit Singh

Abstract


Addition is representative of many arithmetic processing operations that must be carried out in portable digital systems, and the speed and power consumption trade-offs in adder hardware are of interest to portable digital system designers Adders are key components of digital design and architecture and microprocessors. Apart from the basic Addition they also perform other operations such as Subtractions, multiplication, division, address calculation. Adders of various bit widths are frequently required in Very Large Scale Integration (VLSI) circuits from processors to Application Specific Integrated Circuits. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper, different type of 8-bit full adders are analyzed and compared for transistor count, power dissipation, delay and power delay products. The investigation has been carried out with simulation runs on Tanner environment using 180nm & 90nm CMOS process technology at 2V. The result shows that the carry skip adder has the lowest power-delay product.


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