Latency and coherency reduction With Efficient Energy Utilisation using a Novel cache Architecture for NOC circuits

Ashwini Kulkarni, S.P. Mahajan


For Network on Chip (NOC) Circuits where the fast computation and communication is required, memory architecture plays a vital role in deciding the efficiency of computation. Cache is the fastest memory amongst all available memories. Architecture and type of this cache memory has a crucial role to play in NOC circuits. Performance of cache memory plays an important role in deciding the overall performance of NOC circuit. This cache memory suffers with two major problem cache latency and cache coherency.As the number of cores are increasing power consumption of the circuit also increases and becomes a major constrain in the design phase. This paper takes a review of these problems associated with the existing cache memory of NOC chips and suggests a novel architecture of cache model to minimize cache latency and solve the coherency problem.

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